In recent years, semiconductor storage devices (for example, synchronous dynamic random access memories (SDRAMs)) have been used in computers and other information processing apparatus or in various kinds of electronic products such as digital video cameras and digital still cameras.
Further, with the trend toward higher miniaturization and integration levels, semiconductor storage devices employing an open bit line core architecture have come to be provided.
Semiconductor storage devices employing the open bit line core architecture are provided with redundant word lines in addition to real word lines, with provisions made so that the semiconductor storage device may be shipped from the factory after replacing any defective real word line with a redundant word line, for example, at the time of a wafer test or a pre-shipment test.
Here, the real word lines means the word lines for real cells, and the redundant word lines means the word lines for redundant cells.
However, in the prior art, the arrangement of the real word lines and redundant word lines and the power management for the same have not been adequate, and have led to an increase in the area of the memory cell array (core) or an increase in the area and capacity of the power supply used.
For example, in a prior art system, when a block other than those located at an edge of the cell array is selected, one word line rises, but when a block located at an edge is selected, two word lines rise. Therefore, the power supply circuit needs to be designed so that there will be no problem if two word lines rise simultaneously, and this has led to an increase in the area of the power supply.
It has also been practice to provide redundant cells in the bit line direction and to replace any defective cell with a redundant cell, for example, at the time of a wafer test or a pre-shipment test, but since this is not relevant to the present embodiments, no description thereof will be given in this specification.
In the related art, there have been proposed various kinds of semiconductor storage devices employing the open bit line core architecture.    Patent Document 1: Japanese Laid-open Patent Publication No. 2010-027201    Patent Document 2: Japanese Laid-open Patent Publication No. 2001-135075    Patent Document 3: Japanese Laid-open Patent Publication No. 2004-342260